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[VHDL-FPGA-Verilog] uart_0910

Description: uart串口传输的verilog RTL级源码，已通过仿真验证。文件主要包含发送、接受位处理，发送、接受字节帧处理，对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of frame processing, serial communications, a friend of learning helps
Platform: | Size: 7168 | Author: 李鹏 | Hits:

[Crack Hack] TS_Process_V1.0

Description: DVB 加扰软件，对TS流文件进行加扰，符合DVB标准-it s a dvb scramble software . it can scrambling ts stream file ,which apply for dvb standards
Platform: | Size: 80896 | Author: 19869142 | Hits:

[Other] bit_synch

Description: 本人写的MSK解调位同步完整程序，基于QuartusII90环境，采用verilog语言编写，程序简练，可靠性高，而且暂用资源少，适合CPLD器件。文件包含仿真和说明，欢迎下载！-I write a complete program MSK demodulation bit synchronization, based on QuartusII90 environment, using verilog language, procedures, concise, high reliability, and the temporary use, fewer resources for CPLD devices. File contains the simulation and instructions, please download!
Platform: | Size: 320512 | Author: Kerwin | Hits:

[Other] The_Verilog_Hardware_Description_Language

Description: A power point file about Verilog Hardware description language from carnegie mellon university.
Platform: | Size: 234496 | Author: lois | Hits:

[VHDL-FPGA-Verilog] xtp051_sp601_schematics

Description: Xilinx公司最新的Spartan 6系列FPGA所用的开发板电路图，详尽包括了电源、IO、外设、USB等部分的内容，极具有参考价值，另外还有一个USB芯片 68013所使用的HEX文件可供下载-Xilinx' s new Spartan 6 Series FPGA development board used in circuit detail, including the power, IO, peripherals, USB and some other content, most with a reference value, in addition to a USB chip, 68013 using HEX file available for download
Platform: | Size: 311296 | Author: Frank | Hits:

[Windows Develop] LFSR

Description: verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) module. Has passed modelsim simulation.
Platform: | Size: 870400 | Author: 风影 | Hits:

[VHDL-FPGA-Verilog] quaddecoder_verilog_ise11.2_used_09042010

Description: Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descripted in the Constrained file quad.ucf. To use them, you need teh XC9536 and a clock source that s 4 times faster than the fastes signal that the incremental encoder can creates. IThe clock source frequency is uncritical. For manuel rotated incremental encoder like radio VFO oder other tuning knob, a simple TTL oscillator with about 1Mhz (i use 1.8432Mhz and tested 32768Khz) works brilliant. For very fast decoding, this core is not good enought because there are no Filter FlipFlops are programmed to suppress noises on the Channel A/B Lines.-Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descripted in the Constrained file quad.ucf. To use them, you need teh XC9536 and a clock source that s 4 times faster than the fastes signal that the incremental encoder can creates. IThe clock source frequency is uncritical. For manuel rotated incremental encoder like radio VFO oder other tuning knob, a simple TTL oscillator with about 1Mhz (i use 1.8432Mhz and tested 32768Khz) works brilliant. For very fast decoding, this core is not good enought because there are no Filter FlipFlops are programmed to suppress noises on the Channel A/B Lines.
Platform: | Size: 70656 | Author: JUPP | Hits:

[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24

Description: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Platform: | Size: 4946944 | Author: 石 | Hits:

[VHDL-FPGA-Verilog] SinglecycleCPU

Description: 用Verilog实现一个简单的单周期CPU，并运行Quicksort程序以验证正确性。-This file is written in Verilog to achieve a single cycle processor. It can run in Quartus2.
Platform: | Size: 26624 | Author: Matgek | Hits:

[VHDL-FPGA-Verilog] PipelineCPU

Description: 用Verilog实现一个简单的流水线CPU，并运行一个Quicksort程序。这是Berkley，eecs系的计算机系统结构课程实验的实验三。-This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
Platform: | Size: 28672 | Author: Matgek | Hits:

[Other] 2fsk

Description: 2ASK 模块的Verilog实现，附带完整的测试文件-2ASK Verilog module implementation, with a complete test file
Platform: | Size: 3794944 | Author: fqzxw | Hits:

[Other] 2ask

Description: 2ASK 模块的Verilog实现，附带完整的测试文件-2ASK Verilog module implementation, with a complete test file
Platform: | Size: 3272704 | Author: fqzxw | Hits:

[VHDL-FPGA-Verilog] 64B_adder

Description: Verilog HDL 64位并行加法器,并且还含有测试文件，可供测试-Verilog HDL 64-bit parallel adder, and also contains a test file, ready for testing
Platform: | Size: 1024 | Author: xxz | Hits:

[VHDL-FPGA-Verilog] reset

Description: 这是个关于同步复位和异步复位问题的探讨，最后得出同步释放，异步复位的效果最好文件中有编好的verilog文件工程，以及仿真结果和RTL分析图，分析的很详细-This is a synchronous reset and asynchronous reset on the issue of the conclusion that synchronous release, asynchronous reset of the best documents are programmed verilog file works, and simulation and RTL analysis chart, very detailed analysis
Platform: | Size: 549888 | Author: maohuhua | Hits:

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[VHDL-FPGA-Verilog] uart_0910

[Crack Hack] TS_Process_V1.0

[Other] bit_synch

[Other] The_Verilog_Hardware_Description_Language

[VHDL-FPGA-Verilog] xtp051_sp601_schematics

[Windows Develop] LFSR

[VHDL-FPGA-Verilog] quaddecoder_verilog_ise11.2_used_09042010

[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24

[VHDL-FPGA-Verilog] SinglecycleCPU

[VHDL-FPGA-Verilog] PipelineCPU

[Other] 2fsk

[Other] 2ask

[VHDL-FPGA-Verilog] 64B_adder

[VHDL-FPGA-Verilog] reset

[VHDL-FPGA-Verilog] prbs

[VHDL-FPGA-Verilog] bfly_r2dit

[VHDL-FPGA-Verilog] CH375

[VHDL-FPGA-Verilog] lab1_Verilog

[VHDL-FPGA-Verilog] IIR_filter

[VHDL-FPGA-Verilog] verilog

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